library verilog;
use verilog.vl_types.all;
entity dti_up_counter is
    generic(
        IN_WIDTH        : integer := 24;
        OUT_WIDTH       : integer := 8;
        BYTE_ORDER      : integer := 1;
        K               : vl_notype;
        COUNT_WIDTH     : vl_notype
    );
    port(
        pop_clk         : in     vl_logic;
        pop_rst_n       : in     vl_logic;
        pop_req_n       : in     vl_logic;
        fifo_empty      : in     vl_logic;
        count_out       : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of IN_WIDTH : constant is 1;
    attribute mti_svvh_generic_type of OUT_WIDTH : constant is 1;
    attribute mti_svvh_generic_type of BYTE_ORDER : constant is 1;
    attribute mti_svvh_generic_type of K : constant is 3;
    attribute mti_svvh_generic_type of COUNT_WIDTH : constant is 3;
end dti_up_counter;
